1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device and fabrication method thereof which increases a junction breakdown voltage and improves a snap-back characteristic thereof.
2. Description of the Background Art
An integrated circuit unified within a single chip with regard to a control function and a driving function is referred to as a smart power device. An output terminal of the smart power device includes a high power transistor operating at a high voltage of about 15-80V, and a logic unit includes a normal transistor operating at a low voltage of about 5V. Such smart power devices are employed to drive a display apparatus such as LCD (liquid crystal display), and HDTV (high definition TV).
A high power transistor of the smart power device is formed such that a lightly doped region (or, called as drift region) which is lightly doped between a drain and a channel region, compared to the drain.
FIG. 1 is a cross-sectional view illustrating a high power semiconductor device unit of a smart power device according to the conventional art. Therein, a p-channel transistor is shown but an n-channel transistor has the same structure. That is, the conductive type of impurities or ions is opposite and the structure remains identical.
As shown therein, an n-type well 110 is formed in a p-type semiconductor substrate 100. A plurality of field oxide layers 101 are formed on the p-type semiconductor substrate 100 and the n-type well 110. A gate electrode 102 is formed to cover a predetermined portion of the upper surface of the field oxide layer 101 and the n-type well 110. In the n-type well 100 at the sides of the gate electrode 102 there are formed p+ type impurity layers 103a, 103b. The p+ type impurity layer 103a is formed adjacent to an end portion of the gate electrode 102, and the p+ type impurity layer 103a is formed at an end portion of the field oxide layer 101 with the gate electrode 102 laid thereon and spaced from the end portion of the gate electrode 102.
The p+ type impurity layer 103b distanced from the gate electrode 102 is a drain. Also, a p- type impurity layer 104 which is a lightly doped impurity layer in comparison to the source/drain 103a, 103b is extended from a certain point between the field oxide film 101 and the source 103a to an end portion of the drain 103b and covers the drain 103b from bottom and side surfaces thereof. Also, the junction depth of the drift layer 104 remains constant at respective sides of the source and drain. The drift layer serves as a buffer layer when a high electric field is applied to the drain side, thereby preventing a junction breakdown 20 and restraining a hot carrier effect from generating.
However, the semiconductor device as shown in FIG. 1 has disadvantages. That is, since the junction depth of the drift layer is constant, the thickness D1 of the drift layer beneath the drain is relatively thin compared to the thickness D2 of the drift layer beneath the field oxide layer. Accordingly, when high power is applied to the drain region, the electric field loaded at the drain is not sufficiently relieved. Therefore, a junction breakdown easily occurs at the drain region, and the breakdown voltage is relatively low. Further, the snap-back voltage is low due to the hot carrier generation, thereby deteriorating reliability of the semiconductor device.